Sigma-delta modulator

ABSTRACT

A sigma-delta modulator for converting time-discrete samples into corresponding analog signals in, in particular, digital radio communication systems, is characterized by the fact that a first-order sigma-delta modulator is parallelized and a higher-order cascaded sigma-delta modulator is constructed of a number of first-order parallelized structures.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based on and hereby claims priority to PCTApplication No. PCT/DE00/03535 filed on Oct. 6, 2000 and GermanApplication No. 199 48 374.4 filed on Oct. 7, 1999, the contents ofwhich are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

The invention relates to a sigma-delta modulator for convertingtime-discrete samples into corresponding analog signals.

In digital/analog converters such as are used, for example, in digitalradio communication devices, a digital input signal with 2^(n) signalstates and a fixed sampling frequency f_(a) is usually changed into ananalog signal which should correspond as well as possible to the digitalsignal in the frequency range from −f_(a)/2 to +f_(a)/2.

It is particularly at high bit widths n that the number of signal statesto be achieved by analog circuit technology represents a significantproblem. For this reason, a digital signal is interpolated by digitalfilters and so-called sigma-delta modulators are used which distinctlyreduce the bit width n of a digital signal at increased samplingfrequency and transform the quantization noise generated by this intopreviously unused frequency ranges. In this arrangement, structureswhich achieve noise shaping, which are comparable to a shaping which canbe achieved by higher-order IIR (Infinite Impulse Response) filters, areparticularly efficient.

In the case of the sigma-delta modulators, there are two approaches forachieving noise shaping. According to a first approach, higher-orderfeedback loops are used, which allows a reduction to up to two signalstates (1-bit signal technique), but leads to possible instabilities athigh input signals above third-order noise shaping. Excesses very easilyoccur in the range of values. To counteract this, an amplitude-reducedinput signal and state memories with clipping characteristics are usedin practice, which allows an empirically determined stability of thecircuit to be achieved.

According to another approach, first- and/or second-order structures arecascaded which are multi-stage structures and, as a result, exhibit astable operating characteristic.

Known structures of sigma-delta modulators operate serially and at ahigh clock rate, since the sigma-delta modulators are feedbackstructures with non-linear elements. A detailed representation of thetheory and the structure of sigma-delta modulators are provided in S. R.Norswothy, R. Schreier, G. Temes: “Delta-Sigma Data Converters, Theory,Design and Simulation”, IEEE Press 1997, ISBN 0-7803-1045-4.

Due to the noise shaping aimed for, the sigma-delta modulator of atypical digital/analog converter operates in a time- and value-discretemanner at a clock frequency which is much higher than the maximum signalfrequency used. It has feedback filters and nonlinear substructureswhich prevent these structures from being implemented at a lower clockrate.

One aspect of the invention is based on the object of developing astructure for a sigma-delta modulator which operates at a lower clockrate and thus more inexpensively and with power-saving technology.

SUMMARY OF THE INVENTION

According to one aspect of the invention, the object is achieved by afirst-order sigma-delta modulator being parallelized and a higher-ordercascaded sigma-delta modulator being created out of a number ofparallelized first-order structures.

One aspect of the invention achieves the result that sigma-deltamodulators can be achieved which have a lower sampling clock rate andthus less circuit expenditure and are more inexpensive.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects and advantages of the present invention willbecome more apparent and more readily appreciated from the followingdescription of the preferred embodiments, taken in conjunction with theaccompanying drawings of which:

FIG. 1 shows a first-order sigma-delta modulator according to the knownprior art,

FIG. 2 shows a modification of the first-order sigma-delta modulatoraccording to FIG. 1,

FIG. 3 shows a continuing modification of the first-order sigma-deltamodulator with FIR and IIR part-filters,

FIG. 4 shows a continuing modification according to FIG. 3 withtransposed arrangement of the FIR filter (part-filters FIR1, FIR2) withthe adder at the input of the first-order sigma-delta modulator,

FIG. 5 shows a continuing modification according to FIG. 4 withcombining of the output signals from the IIR and FIR2 filter,

FIG. 6 shows a continuing modification of a first-order sigma-deltamodulator according to FIG. 5 with combining of the part-filter FIR2 andof the quantizer to form a multi-bit quantizer,

FIG. 7 shows a continuing modification of a first-order sigma-deltamodulator according to FIG. 6 with replacement of the part-filter FIR1by an Integrate &- Dump filter,

FIG. 8 shows an arrangement of a first-order sigma-delta modulatoraccording to FIG. 7 which is expanded for calculating missing truthvalues of the quantization error,

FIG. 9 shows a structure according to one aspect of the invention of aparallelized first-order sigma-delta modulator,

FIG. 10 shows modules drawn out of FIG. 9,

FIG. 11 shows an implementation according to one aspect of the inventionof a higher-order sigma-delta modulator cascaded from three stages of afirst-order sigma-delta modulator,

FIG. 12 shows a logic module for the first stage of a sigma-deltamodulator for determining the values of the quantizer from thequantization error and the input signal, and

FIG. 13 shows a logic module for the second and subsequent stages of asigma-delta modulator for determining the values of the quantizer fromthe quantization error and the input signal.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Reference will now be made in detail to the preferred embodiments of thepresent invention, examples of which are illustrated in the accompanyingdrawings, wherein like reference numerals refer to like elementsthroughout.

One aspect of present invention is based on a known first-ordersigma-delta modulator as shown diagrammatically in FIG. 1. Withoutrestricting the generality of the invention, the input signal x(k) willbe normalized to the range of numbers −1≦x(k)≦1 and the step height ofthe quantizer will be assumed to be 2/(L−1) in the subsequentdiscussion, where L specifies the number of quantization levels. Thedigital sigma-delta modulator converts the digital input signal x(k)into a 3-step (1.5 bit) data stream as output signal y(k). It should beclear that any type of quantizer or something equivalent can be used forperforming the conversion into a quantized digital data stream.

The digital input signal x(k) is input into an adder 1, the output ofwhich is conducted to a delay circuit 2. The output of the delay circuit2 is conducted to an adder 3 and, at the same time, to the input of adecision circuit 4 in which the signal {tilde over (x)} (k), delayed inthe delay circuit 2 by one clock unit compared with the signal x(k), isquantized into the specified number of quantization levels which arerestricted to the set (−1, 0, +1) in the example. In the adder 3, aquantization error signal e(k) is formed from the sum of the outputsignal {tilde over (x)} (k) of the delay circuit 2 and the negatedoutput signal y(k) of the decision circuit 4 due to the nonlinearalityof the quantizer, which quantization error signal is supplied to theadder 1 at the input of the delay circuit 2 for the purpose of additionto the input signal x(k).

According to FIG. 2, the known first-order sigma-delta modulatoraccording to FIG. 1 is changed in a first step into a first-order IIR(Infinite Impulse Response) filter (delay circuit 2, adder 1, feedbackbranch) which can be considered as an integrator, and into a decisioncircuit 4. IIR=Infinite Impulse Response Filter (digital filter withinfinite impulse response).

The input signal x(k) is fed via the integrator into the decisioncircuit 4 and the quantized output signal y(k) is conducted back to theinput in order to be subtracted from the input signal x(k). The signal{tilde over (x)}(k), delayed by one clock unit, is directly conductedvia a feedback branch to the adder 1 which is also supplied with thedifference from the input signal x(k) at the output signal y(k) which isformed in the adder 3.

Such a sigma-delta modulator is described on page 6 of the IEEEpublication initially designated and is shown there as a block diagramin FIG. 1.4.

In a next step, the first-order IIR filter according to FIG. 2 is splitinto an FIR filter 5 and an IIR filter (delay circuit 2, adder 1,feedback branch), which operates at a lower clock rate. Equation (1)specifies how the transfer characteristic of the IIR filter can be splitinto the two part-filters FIR and IIR: $\begin{matrix}{\frac{1}{1 - {az}^{- 1}} = {( {\sum\limits_{v = 0}^{\lambda - 1}{a^{v}z^{- v}}} )\frac{1}{1 - {a^{\lambda}z^{- \lambda}}}}} & (1)\end{matrix}$

where z=exp (jωT),

α=pole point of the first-order IIR filter

λ=clock ratio between output and input clock

An FIR (Finite Impulse Response) filter is a filter with infiniteimpulse response and is characterized by a high stability.

In the case of an integrator as used in FIG. 2, the pole point is α=1and equation (1) can be changed into equation (2): $\begin{matrix}{\frac{1}{1 - z^{- 1}} = {( {\sum\limits_{v = 0}^{\lambda - 1}z^{- v}} )\frac{1}{1 - z^{- \lambda}}}} & (2)\end{matrix}$

A structure according to FIG. 3 is obtained, with two part-filters FIRand IIR. The FIR filter 5 is arranged between the adders 3 and 1. If theinput signal {overscore (χ)}(k) of the two implementations of the IIRfilter is the same, the same output signal {tilde over (x)}(k) is alsoobtained.

The processing of the values in the FIR filter 5 and the addition in theadder 3 are linear operations, which is why filter 5 and adder 3 can betransposed. This is shown in FIG. 4. The FIR filter 5 is stripped intotwo FIR part-filters (FIR1, FIR2) 5 a, 5 b in order also to include thebranch from output signal y(k) to adder 3 in accordance with itsfunctions.

In a next step, the output signals from the IIR filter (delay circuit 2,adder 1, feedback branch) and FIR2 filter 5 b according to FIG. 5 arecombined again in the adder 3.

In the filter FIR2 5 b, the last λ−1 decision circuit output values areadded. If the quantizer uses L steps, the signal at the output of thefilter FIR2 5 b has (L−1)λ+1 steps. Thus, the combination of FIR2 5 band decision circuit 4 can be considered as a multi-bit quantizer 4*.

In accordance with the derivation conducted above, FIR1 filter 5 a andIIR part-filters (delay circuit 2, adder 1, feedback branch) in FIG. 6reproduce an integrator as used in FIG. 1. In both cases, a multiple ofthe quantization level is subtracted from the integration result. Sincethe quantization error is restricted to the same unambiguous range bothin the structure shown in FIG. 6 and in the structure of a sigma-deltaconverter shown in FIG. 1, the quantization error of the structures ofFIG. 1 and FIG. 6 is identical.

 e ₂₍(k)=e(k)  (3)

In the part-structure with feedback of FIG. 6, a delay by λ instants isperformed. If it is intended to determine the quantization error valuese₂(k) only sub-sampled every λ instants, the calculation can beperformed at low clock rate: the part-filter FIR1 5 a is replaced by anintegrate&dump filter 6 and the time delay of the low clock rate isused. This is illustrated in FIG. 7.

Using the sigma-delta modulator developed further according to FIG. 8provides interpretation nodes for the truth values of a modulatoroperating at a high clock rate (clock rate k₂=λk). The missing truthvalues of the quantization error (e₂(k₂+1), e₂(k₂+2), . . . ) can bederived free of recursion from the parallelized arrangement; they are nolonger included in the recursion loop which leads from the output of themulti-bit quantizer 4* to the adder 1. The quantization error e₂(k₂) isconducted to an adder 7 arranged between a downstream delay circuit 2′and a multi-bit quantizer 4′* for calculating the quantization errorvalue e₂(k₂+1) following in time. In addition, the negated output signaly(k₂+1) of the multi-bit quantizer 4′* is input to another adder 8 whichforms from this and from the output signal of the adder 7 the errorsignal e₂ (k₂+2). This process is repeated for all truth values of thequantization error e₂(k₂+1) . . . e₂(k₂+λ−1) to be calculated.

From the values of the quantization error e₂(k) and of the input signalx(k), the numerical value of the quantizer 4 can be calculated by alogic:

y(k)=e ₂(k−1)+x(k)−e ₂(k)  (4)

In the figures following, the implementation of a parallelized cascadedthird-order sigma-delta modulator with output values of −4 . . . +4 anda factor λ=16 is shown as an example of an application. Each first-ordersubsystem of this parallelized cascaded sigma-delta modulator generates16 3-level (1.5 bit) output signals. However, the application of thestructures shown here is obviously not restricted only to the specialcases of 1.5 bits and λ=16.

The following representation is based on the parallel implementation ofa first-order sigma-delta modulator shown in FIG. 9. The 16 inputsignals of this example are combined in the signal err 1. These signalsare separated by the demultiplexer Demux and subsequently supplied tothe individual demultiplexers Demux b 0 . . . 15.

These demultiplexers separate their respective input signals into twopart-signals:

One part-signal (sgn) includes the most significant bit (MSB) and thesecond most significant bit (2nd) MSB and is supplied to the logicblocks b 0 . . . 15 time-delayed via Mux, delay elements and Demux c.

A second part-signal (amp) includes the input signal of thedemultiplexer Demux b, reduced by the MSB, and is fed into an arithmeticlogic unit.

As can be seen from the subsequent transformation, the splitting resultsin a reduction of the 3-level first-order sigma-delta modulator to apart-signal and a first-order 2-level sigma-delta modulator, which issimple to achieve:

Let the input signal be normalized to the range of numbers −1<x(k)≦1without restriction of its generality. Then, x(k) can be represented asfollows:

x(k)=amp(k)+s(k)  (5)

where

s(k)ε  (6)

and

0≦amp(k)<1  (7)

holds true. The equation of a 1.5-bit quantizer $\begin{matrix}{{y(k)} = \{ \begin{matrix}1 & {{{{if}\quad {e( {k - 1} )}} + {x(k)}} \geq 0.5} \\\begin{matrix}{- 1} \\0\end{matrix} & \begin{matrix}{{if}\quad {e( {{k - {1\_} + {x(k)}} < {- 0.5}} }} \\{else}\end{matrix}\end{matrix} } & (8)\end{matrix}$

can thus be transformed into: $\begin{matrix}{{y(k)} = \{ \begin{matrix}1 & {{{{if}\quad {e( {k - 1} )}} + {{amp}(k)}} = {{s(k)} \geq 0.5}} \\{- 1} & {{if}\quad {e( {{k - {1\_} + {{amp}(k)} + {s(k)}} < {- 0.5}} }} \\0 & {else}\end{matrix} } & (9)\end{matrix}$

The quantization error e(k) of the first-order 1.5-bit sigma-deltamodulator is restricted to the range of values −0.5≦e(k)<0.5. Since onlys(k) can cause the threshold −0.5 to be exceeded, it follows that:$\begin{matrix}{{y(k)} = {{s(k)} + \{ \begin{matrix}1 & {{{{if}\quad {e( {k - 1} )}} + {{amp}(k)}} \geq 0.5} \\0 & {else}\end{matrix} }} & (10)\end{matrix}$

FIG. 9 shows the parallelization of the 1-bit sigma-delta convertersection according to FIG. 8. The integrate&dump filter and the multi-bitsigma-delta modulator are emphasized by shading. The overflowcharacteristic of the twos complement arithmetic is utilized asquantizer. The structures not emphasized calculate the abovementionedtruth values of the quantization error of the sigma-delta modulator.From the quantization error and knowledge of the input signal which isforwarded by delay circuits from the multiplexer MUX to thedemultiplexer DEMUC c (center FIG. 10), the values of the quantizer aredetermined by a logic which is shown in greater detail in FIG. 13 andFIG. 14.

The allocations of the terminals of the elements used: delay circuitwith one input and one output, Demux b with one input and two outputs(In 1, s gn, amp), adder with two inputs and one output (In 1, In 2,Out), logic b with three inputs and two outputs (z sum x, sum x, x, ylneg, y2 pos) from FIG. 9 are shown in greater detail in FIG. 10.

The delay circuit used in FIG. 9 holds the value of its input signal forone unit of time.

The function of Demux b has already been discussed above: onepart-signal (s gn) includes the MSB and the 2nd MSB and is supplied witha time delay via Mux, delay elements and Demux c to the logic blocks b 0. . . 15. A second part-signal (amp) includes the input signal of thedemultiplexer Demux b reduced by the MSB and is fed into an arithmeticlogic unit.

A wrap-around adder with L−1 stages is used.

The logic b reproduces the function of equation 4. It is shown again ingreater detail in FIGS. 12 and 13.

FIG. 11 shows the overall model in which 3 stages of a parallelizedfirst-order sigma-delta modulator are cascaded to form a third-ordersigma-delta modulator. The three cascades are shown underneath oneanother. The system resembles a system of cascaded sigma-deltamodulators without parallelizing. The digital input signal x(k) isconducted to the first stage—a parallelized first-order sigma-deltaconverter according to FIG. 9—which converts the digital input signaloutput by the interpolation filter into a digital parallel m-bit datastream Y1 at the output (m≧1). The output error signal e2(k₂) from theoutput err 1 of the first sigma-delta modulator is supplied to thesecond cascade (illustrated in the center in FIG. 11) analogously toFIG. 8 and FIG. 9, and is processed there in the same manner etc.

The output signals from output Y2 are filtered by the FIR filter:

H ₁(z)=1−z ⁻¹  (11)

and those from output Y3 are filtered by the FIR filter:

H ₂(z)=(1−z ⁻¹)  (12)

and combined to form an output signal of the third-order sigma-deltaconverter y₃(k). $\begin{matrix}{{y(k)} = \{ \begin{matrix}{- 1} & {if} & {( {( {{e(k)} \geq 0} )( {{e( {k - 1} )} < 0} )( {{x(k)} < 0} )} )( {( {{e(k)} \geq 0} )} } \\\quad & \quad & { ( {{x(k)} < {- 0.5}} ) )( {( {{e( {k - 1} )} < 0} )( {{x(k)} < {- 0.5}} )} )} \\1 & {if} & ( {( {{{e(k)} < 0}( {{e( {k - 1} )} \geq 0} )( {{x(k)} \geq 0} )} )}  \\\quad & \quad & {( {( {{e(k)} < 0} )( {{x(k)} \geq {- 0.5}} )} )( {( {{e( {k - 1} )} \geq 0} )( {{x(k)} \geq {- 0.5}} )} )} \\0 & {else} & \quad\end{matrix} } & (13)\end{matrix}$

FIG. 12 shows the internal configuration of a logic b element in detailfor the first stage of the sigma-delta modulator from FIG. 9 and FIG.11, respectively. In this configuration, the function of equation (4) isimplemented. The output signal of the quantizer 4 only has the threestates −1, 0, 1. To identify the respective state, it is not necessaryto execute the addition or subtraction exactly. Instead, it issufficient to provide information on the range of numbers in whiche₂(k), e₂(k−1) or x(k) is located:

FIG. 13 shows the internal configuration of a logic b element in detailfor the second and subsequent stages of the sigma-delta modulator fromFIG. 11. The error signal from preceding stages is restricted to therange −0.5≦e(k)<0.5, so that some logic operations from equation 13 andFIG. 12 are not necessary.

The invention has been described in detail with particular reference topreferred embodiments thereof and examples, but it will be understoodthat variations and modifications can be effected within the spirit andscope of the invention.

What is claimed is:
 1. A sigma-delta modulator for converting a digitalinput signal into a quantized output signal, comprising: a first-ordersigma-delta modulator, comprising: a first adder receiving a modulatorinput signal and a first quantization error value, forming a firstaggregate signal, a first delay circuit receiving the first aggregatesignal and delaying the first aggregate signal by one clock unit, adecision circuit receiving the delayed first aggregate signal andoutputting the quantized output signal, and a second adder receiving thedelayed first aggregate signal from the first delay circuit and thequantized output signal and negating the quantized output signal,forming the first quantization error value; and a plurality of nparallelized branches, each branch receiving the digital input signal, afirst branch of the n branches comprising the first-order sigma-deltamodulator and outputting the quantized output signal and a firstquantization error value, and each branch of the n branches, other thanthe first branch, comprising: a second delay circuit receiving thedigital input signal and delaying the digital input signal by i−1 clockunits, where 1<i<=n, a switch receiving, and temporally sampling, thedelayed digital input signal, a third adder receiving the sampled signaland a second quantization error value from the preceding branch, forminga second aggregate signal, a multi-bit quantizer receiving the secondaggregate signal from the third adder and outputting an output signaldelayed by i−1 clock units, and a fourth adder receiving the outputsignal, negated, from the multi-bit quantizer and the second aggregatesignal from the third adder, forming the second quantization errorvalue.
 2. The sigma-delta modulator as claimed in claim 1, wherein: thefirst branch comprises an Integrate&Dump filter receiving the digitalinput signal in series with another switch, the other switch providingthe modulator input signal to the first adder; the decision circuit ofthe first-order sigma-delta modulator is another multi-bit quantizer;and the first quantization error value is provided to the third adder ofa second branch of the n branches.
 3. The sigma-delta modulator asclaimed in claim 2, wherein the Integrate&Dump filter, each of themulti-bit quantizers, and each of the quantization error values arearranged as a binary tree.
 4. The sigma-delta modulator as claimed inclaim 1, wherein the quantized output signal is calculated from thefirst quantization error value, the second quantization error values,and the digital input signal.
 5. The sigma-delta modulator as claimed inclaim 1, wherein the first quantization error value and the secondquantization error values are each calculated as sub-sampled values andcorrespond to a quantization error value calculated at a higher samplingrate by a non-parallelized sigma-delta modulator.
 6. The sigma-deltamodulator as claimed in claim 1, wherein a plurality of sigma-deltamodulators are cascaded in stages, forming a higher-order sigma-deltamodulator.
 7. A sigma-delta modulator for converting a digital inputsignal into a quantized output signal, comprising: a first-ordersigma-delta modulator; and a plurality of n parallelized branches, eachbranch receiving the digital input signal, a first branch of the nbranches comprising the first-order sigma-delta modulator and outputtinga first quantized output signal and a quantization error value, and eachbranch of the n branches, other than the first branch, comprising: adelay circuit receiving the digital input signal and delaying thedigital input signal by i−1 clock units, where 1<i<=n, a switchreceiving, and temporally sampling, the delayed digital input signal, afirst adder receiving the sampled signal and a second quantization errorvalue from a preceding branch, forming an aggregate signal, the firstadder of a second branch of the n branches receiving the firstquantization error value from the first branch; a multi-bit quantizerreceiving the aggregate signal from the first adder and outputting anoutput signal delayed by i−1 clock units, and a second adder receivingthe output signal, negated, from the multi-bit quantizer and theaggregate signal from the first adder, forming the second quantizationerror value.